1. Field of the Invention
The invention relates to a motor drive, and more particularly to a drive method and system for a permanent magnet surface-mount (PMSM) motor utilizing a space-vector PWM modulation scheme.
2. Description of the Related Art
Three-phase motor drives utilizing inverters are well known in the industry. Typically a DC bus supplies switched power to different phases of an AC motor. For supplying switching commands and sequences to the inverter, sensorless vector control is achieving wide attention. Sensorless control eliminates speed, flux and torque sensors and replaces them with DSP-based estimation based on the measured terminal voltages and currents. Thus, the cost of the drive is reduced and reliability is enhanced. A DSP-based motor drive of background interest is described in the present inventor""s U.S. Application Serial No. 60/465,890 filed Apr. 25, 2003; and Ser. No. 10/294,201 filed Nov. 12, 2002, incorporated by reference. However, the estimation algorithms tend to be complex, particularly at low frequencies.
Space-vector pulse-width modulation (SVM) has become a popular form of pulse-width modulation (PWM) for voltage-fed converter drives because of its superior harmonic quality and extended linear range of operation. SVM arrangements of background interest are described in Ser. No. 10/402,107 filed Mar. 27, 2003, incorporated by reference.
However, one problem of SVM is that it requires complex on-line computation that usually limits its operation to switching frequencies of up to several kilohertz (e.g. about 10 kHz). Switching frequency can be extended by using high-speed DSP and simplified algorithms including lookup tables (LUT). Power semiconductor switching speeds, particularly in IGBT""s, have been improving dramatically. However, the use of LUT""s, unless very large, tends to reduce pulse-width resolution.
The present invention avoids the intensive calculations such as arctan and square root functions and lookup tables in the conventional space vector PWM modulation scheme. An algorithm structure is proposed for the implementation of a versatile space vector PWM scheme, which can generate both 3-phase and 2-phase SVPWM without intensive math functions or lookup tables. This structure supports overmodulation, symmetrical PWM and asymmetrical PWM modes.
The invention implements a versatile 2-level space vector PWM (SVPWM) modulator, which allows 3-phase and 2-phase modulation algorithms to be implemented in a common algorithm structure. The implementation utilizes mainly decision logic and does not require any intensive math functions such as arctan, sine, cosine and/or square root functions. The algorithm provides overmodulation, symmetrical and asymmetrical mode capabilities.
The invention provides a space vector pulse-width modulator and a method implemented by the modulator.
According to an aspect of the invention, a space vector pulse-width modulator (SVPWM) may comprise a precalculation module which accepts Ua and Ub modulation indexes and in response thereto, outputs modified Ua and Ub information.
According to another aspect of the invention, a SVPWM may comprise a sector finder having a U module which receives Ua or modified Ua information and outputs a U sector; and a Z module which receives the U sector and Ub or modified Ub information and outputs a Z sector; said U sector and said Z sector being 2-phase control signals for implementing 2-phase modulation.
According to another aspect of the invention, a SVPWM may comprise, for 3-phase modulation, an active vectors calculation module and an assign vectors module which receive Ua and Ub or modified Ua and Ub information and a U sector, and which calculate active vectors for 3-phase modulation; a zero vector selector which receives said Z sector and calculates zero vectors for 3-phase modulation; and a PWM counter block which receives said active vectors and zero vectors and outputs 3-phase control signals for implementing 3-phase modulation.
The PWM counter block preferably has a symmetrical PWM mode, an asymmetrical PWM mode, or both.
The SVPWM may further comprise a rescale and overmodulation module which receives duration information corresponding to vectors and in response thereto, detects the occurrence of overmodulation. Overmodulation is preferably detected in response to a negative zero vector time. The module may respond to overmodulation by clamping a zero vector time to zero and rescaling active vector times to fit within a PWM cycle.
Said resealing may restrict a voltage vector to stay within hexagonal boundaries on the space vector plane, while preserving voltage phase.
According to another aspect, the invention provides a method carrying out at least the steps outlined above.
Other features and advantages of the present invention will become apparent from the following description of embodiments of the invention which refers to the accompanying drawings.